Abstract

Thewide utilization & acceptance of low power devices leads to drastic growthin the miniaturization of electronic. The performance of these low powerdevices on par with the efficiency, But the limitations of the devices are onlypower and delay, as the devices are operating under the sub threshold operations.SRAM is one of the major component in digital design, occupies 50%  in area and consumes nearly 40% of power. Inthis paper a novel sub threshold SRAM designs have proposed to improve thestability in read & write operations along with power and delay. The mainfocus of this research work is to address the leakage power, when the circuitsare operating under the sub threshold region. The critical limitation in thisdesign is the leakage power as the technology is increasing. As the technology increasing at a rapid ratethe leakage power is dominating the dynamic power. This amount of power need tobe controlled at all the levels of abstractions in the entire design. Anotherissue is with the delay, where this leads to reduce the speed of operation. Thisresearch work describes the two novel proposed designs which may be helpful toimplement SRAM, to satisfy the above requirement. i.e. Sub threshold Schmitttrigger based SRAM & source coupled logic based SRAM. The first part of thepaper describes the design and implementation of sub threshold Schmitt triggerbased SRAM and analyzing the performance by write & read operations,performance through power and delay. In the second part, analysis of sourcecoupled logic functionally and performance is analyzed and estimated, finallymade a comparison between these two novel designs in power and delay under subthreshold operation. Conclusion is made based on the experimental resultsobtained for high frequency, low power electronics.     

Keywords: Schmitt triggered  SRAM, Source coupled  SRAM, Lekage power,Subthreshold operation,Designs, Bistable latch