Abstract

AbstractThe emerging technology of reversible circuits offers a potential solution tothe synthesis of ultra low-power quantum computing systems. A reversiblecircuit can be envisaged as a cascade of reversible gates only, such as Toffoligate, which has two components: k control bits and a target bit (k-CNOT), k ≥1. While analyzing testability issues in a reversible circuit, the missing-gatefault model is often used for modeling physical defects in quantum k-CNOTgates. In this paper, we propose a new design for testability technique for quantumreversible circuits in which the gates of a circuit are grouped into differentsets and the gates from each set are attached to an additional input line viaan extra control. Such arrangement makes it possible to test the gatesbelonging to a set separately. Our algorithm exploits the feature of manyreversible circuits in which the high quantum cost gates have target on thesame line and this line is devoid of any control of other gates. All thesegates skip addition of extra control for testing. The proposed technique offersless quantum cost in comparison to other DFT techniques published so far.Testing is an essential step that ensures the designed circuit realizes desiredfunctionality. Testing an integrated circuit is the time-consuming task nowadays.Different methods are needed to get shorter test time. This paper presents anoriginal approach and a practical system for implementation and testing ofreversible logic. These testing methods, based on DFT (Design for testability)techniques. Reversible ALU is a testing circuit in this process. This ALU istested by using two techniques of DFT which improves the controllability andobservability of internal nodes, so that embedded functions can be tested. Anode is said to be testable if it is easily controlled and observed. Thetechniques are 1) Ad hoc method and 2) Simple BIST (Built-in self-test) method,BIST belongs to the structured technique of DFT. This design is with VerilogHDL and simulated using ISIM simulator and implemented on Spartan3E (XC3S500E-FG320-5)FPGA. This proposed designed architecture provides delay of 41.054ns for SimpleBIST and 40.774ns for Ad-hoc test methods, with an area coverage of 7% and 5%on Spartan 3E implemented by using Xilinx ISE Design Suite.

 Keywords: DFT (design for testability),Simple BIST (Built- In-Self Test), Reversible Logic