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HIGH PERFORMANCE, LOW POWER ARCHITECTURE OF 5-STAGE FIRFILTER USING MODIFIED COMPRESSOR WITH MONTGOMERYMULTIPLIER

Abstract

Abstract: The digital world continues to witness an unprecedented growth in view of the technological advancements in thefield of Digital Signal Processing (DSP). The increased usage of digital applications along with the tremendous evolution ofVery Large Scale Integration (VLSI) technology over a few epochs has led to the development of enhanced algorithms andarchitectures for DSP systems that augur to meet the demands of a wide variety of applications in this expanding horizon ofthe signal processing sector. Finite Impulse Response (FIR) digital filter is the most potent and frequently used component invarious signal processing and image processing applications. Since the intricacy of implementation grows with the filter orderand the precision of computation, real-time realization of these filters with desired level of accuracy and less area-delay-powercomplexity is a challenging task.Multiplication is one of the most extensively used arithmetic operations in a wide range ofapplications, such as multimedia processing and artificial neural networks. For such applications, multiplier is one of the majorcontributors to the energy consumption, critical path delay and resource utilization. These effects get more pronounced inFPGA-based designs. However, most of the state-of-the-art designs are done for ASIC-based systems. Further, few FPGAbased designs that exist are largely limited to unsigned numbers, which require extra circuits to support signed operations. Toovercome these limitations for the FPGA-based implementations of applications utilizing signed numbers, this paper presentsan area-optimized, low-latency and energy-efficient architecture for accurate signed multiplier. Based on these objectives, manyalgorithms and architectures have been proposed for FIR filters. The goal of this project is to demonstrate the work method ofa simple Firstorder FIR filter by showing the results in a Vector Waveform simulation. FIR filter is a digital filter. Time delaygives the information of speed. FIR filter which has minimum time delay gives better response than others. Area utilization andtime delay are two important factors to design any filter. The important advantage of FIR filter on FIR filter is itsimplementation efficiency. FIR filters require less number of orders as comparison to meet same specification. FPGA providesmore logic flexibility and the power consumption is low. FPGA is a semiconductor device containing programmable logiccomponents and programmable interconnects.

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