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ULTRA-LOW-VOLTAGE GDI-BASED HYBRID FULL ADDER DESIGNFOR AREA AND ENERGY-EFFICIENT COMPUTING SYSTEMS

Abstract

Abstract: In Integrated circuits(IC) s system Computational performance is limited by its performance and since the executiontime is dominated by the multiplication factor because of that high speed adder is much more important in DSP systems. Thispaper presents an efficient full adder design in CMOS 25nm technology using footed quasi resistance based gate diffusioninput (FQR-GDI). This design uses less number of transistors than the conventional CMOS based Adder designs. By employingthe FQR-GDI technique there is an extensive decrease in power and delay of the circuit. Design also solves the threshold dropsproblem of Original GDI cell resulting in better output signals. The proposed methodology implemented in Tanner Tools usingTSMC library.

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Department of Civil Engineering, Amity University Haryana,




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