Abstract: One of the major problems in communication is the secure transportation of data over communication protocols.
This paper presents a feasible resolution for Rijindael’s encryption and decryption using VHDL for FPGA (cyclone III) &‘C’
running over Nios II processor. The Nios II is a versatile embedded processor which is high performance, of lower cost and
power consumption, has low complexity combining several functions into one FPGA. This paper shows implementation of
AES algorithm for 128 bit data and 128 bit key in RTL (VHDL) and its software implementation using C. To measure
performance in same system that is same hardware Nios II soft core processor is used. Hence this paper shows application of
Advance Encryption Standard (AES) algorithm in UART for secure transfer of data in software and hardware platforms
which are (RTL)VHDL and ‘C’ and further to decide suitability of its implementation of specific platform( software or
hardware) depending on different baud rates supported by UART. The results are compared with the help of tools modelsim
(Quartus II) and Nios II 10.1 software build
Tools for eclipse
Keywords- AES,VHDL, FPGA ,RTL