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DESIGN OF EFFICIENT COMPARATOR USING MAJORITY LOGIC FORMULATION 

Abstract

Abstract: Majority gateand inverter are the basic logic units of Quantum-dot Cellular Automatacircuits. Most former comparators are designed in three-input majority gatesand inverters. In this paper, a design of efficient comparator using majoritylogic formulation is presented. The proposed comparator is simulated in QCADesigner and the result shows that the logic function of proposed comparator isbetter in all aspects.


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