Abstract

Abstract: Inthis work, an efficient new modular multiplication method for {2^k−1, 2^k, 2^k+1−1} moduli set is proposedto implement a residue number system (RNS)-based fixed coefficient finiteimpulse response filter. The new multiplication approach reduces the number ofpartial products by using pre-loaded product block. The reduction in partialproducts with the proposed modular multiplication improves the clock frequencyand reduces the area and power as compared with the conventional modularmultiplication. Further, the present approach eliminates a binary number toresidue number converter circuit, which is usually needed at the front end ofRNS-based system. In this work, two fixed coefficient filter architectures withthe new modular multiplication approach are proposed. The filters areimplemented using Verilog hardware description language. The UnitedMicroelectronics Corporation 90 nm technology library has been used forsynthesis and the results area, power and delay are obtained with the help ofCadence register transfer level compiler. The power delay product (PDP) is also considered forperformance comparison among the proposed filters. One of the proposedarchitecture is found to improve PDP gainby 60.83% as compared with the filter implemented with conventional modularmultiplier. The filters functionality is validated with the help of Altera DSPBuilder.

Keywords: FIR filter, residue number system, shift add approach, pre-loaded product, modular multiplication