Abstract

Abstract Thisarticle presents the first compact hardware implementation of a digitalcode-shifted reference (CSR) ultrawideband (UWB) transceiver. The security ofthe transmission is based on changing the physical properties of thetransmission without the use of higher level security options. The softwaremodels of the designed transceiver are simulated and verified in bothfloating-point and fixed-point numerical representations. The synthesizableVerilog description of the transceiver architecture is simulated and verifiedagainst its fixed-point simulation model. The secure transceiver is implementedon our custom-developed field-programmable gate array (FPGA) board. Thecharacteristic and implementation results of the secure transceiverarchitecture on the FPGA are presented. The bit error rate performance of thetransceiver is measured in realtime on the FPGA using an accurate on-chipGaussian noise generator and is compared with that of the software simulationmodel. An ASIC architecture of the CSR-UWB transceiver is estimated to occupy0.019 mm2 and dissipate .63 mW from a 1-V supply while operating at 82 MHz in astandard 32-nm CMOS technology.

Keywords:Code-shiftedreference ultra-wideband (CSRUWB), field-programmable gate array (FPGA),baseband architecture